The present invention relates to semiconductor design technology, and more particularly to an output driver of a semiconductor memory device.
In general, semiconductor memory devices such as a dynamic random access memory (DRAM) select one of a plurality of cell capacitors according to X and Y address signals inputted from the outside. And then, the semiconductor memory devices amplify a voltage level corresponding to charges stored in the selected cell capacitor and transfer the amplified voltage level to the outside as an output data in a read operation. On the contrary, in a write operation, the semiconductor memory devices store a voltage level corresponding to an input data in the selected cell capacitor in the form of charges, wherein the input data is provided from the outside simultaneously with X and Y address signals.
The semiconductor memory devices include a variety of paths and circuits in order to quickly access a desired cell among the plurality of cell capacitors and amplify a fine signal of the accessed cell accurately and quickly. For example, the semiconductor memory devices need an output driver for processing a data DQ and a data strobe DQS as a main data output driver is needed for transferring an amplified signal from a memory cell to global I/O (GIO) line at a read operation.
FIG. 1 illustrates a schematic circuit diagram of a conventional output driver in a semiconductor memory device. The output driver is used for processing an internal data at a read operation.
Referring to FIG. 1, the output driver is provided with two output driving element for outputting a data DQ which is read from a cell. A first output driving element including a PMOS transistor MP1 is a kind of pull-up driver for outputting a high level of data in a pull-up method. A second output driving element including a NMOS transistor MN1 is a kind of pull-down driver for outputting a low level of data in a pull-down method.
Not shown in FIG. 1, pull-up and pull-down pre-driving elements are further provided. The pull-up pre-driving element is provided for driving the first output driving element and the pull-down pre-driving element is provided for driving the second output driving element.
The output driver configured as the above-mentioned includes the first and second output driving elements in a kind of inverter form, but having different input signals. A supply voltage level terminal VDDQ and a ground voltage level terminal VSSQ defined for an output on JEDEC spec are used.
At an interface terminal between a main memory of the DRAM and a chip set, voltage level swings range from a low level to a high level centering around a termination voltage level VTT which is a half of a supply voltage level VDDQ/2. Accordingly, in case that the output driver is used in the main memory, an output data DOUT is outputted as low or high data centering around the termination voltage level VTT, referring to FIG. 2. FIG. 2 illustrates a signal timing diagram of an output of the conventional output driver.
For driving the output driver operating as describe above, a general inverter is used which swings from the ground voltage level VSSQ to the supply voltage level VDDQ fully as a pre-driver. In this case, there is a problem such that a first output date is deteriorated.
Referring to FIG. 2, it is clearly confirmed by comparing a starting point of the first output data with that of a second to a fourth output data. Comparing a gate voltage of the PMOS transistor MP1 or the NMOS transistor MN1 when the output data DOUT is in the termination voltage level VTT, the gate voltage of the PMOS transistor MP1 is the half of the supply voltage level VDDQ/2 at the starting point of the first output data, however, at the starting point of the second to fourth output data, the supply or ground voltage level VDDQ or VSSQ is supplied to a gate of the PMOS transistor MP1. The voltage difference causes a current difference of the output driver.
In addition, if it is assumed that a threshold voltage of the PMOS and NMOS transistor MP1 and MN1 should be half the supply voltage level VDDQ/2, a first data eye is reduced due to deterioration in a slew rate or a duty cycle, comparing the other. The reason that the slew rate or duty cycle is deteriorated is that the first output data is processed when the PMOS transistor MP1 begin to turn on. Comparing with the first output data, the second to fourth output data are processed after the PMOS and NMOS transistors MP1 and MN1 fully turn on because the supply or ground voltage level VDDQ or VSSQ is supplied to each transistor at the starting point of each output data.